A semiconductor chip is an array of devices with conducting terminals that are interconnected by wiring patterns of metal strips. In Very Large Scale Integration (VLSI) chips, these metal wiring patterns are multilayered. Each wiring layer is separated from other conducting layers by layers of insulating material. Interconnections between different wiring pattern layers are made through holes (vias) that are etched through the insulating material layers.
As VLSI chip features shrink and the number of wiring layers increases, surface irregularities in each layer translate to subsequent layers, making each subsequent layer's surface even more irregular. These irregularities distort shapes formed on the surface, making level to level alignment difficult. In some cases, this distortion is so severe as to make it nearly impossible to adequately replicate (print) the intended shape or align printing masks to previous levels.
One prior art way surface irregularities were reduced was to fill the vias with conducting material (i.e., form studs in the vias) before printing the wiring pattern on the surface. However, the raised wire shapes on the surface still left irregularities in subsequent surfaces. Therefore, techniques were developed that are used at various levels to create a nearly perfectly flat, or, planar surface, so that shapes are printed with high dimensional and geometric accuracy. These techniques are known, in the art, as planarization.
One such planarization process is Chemical-Mechanical Polishing, also known as Chem-Mech Polishing or CMP. CMP involves applying an abrasive in a dispersion (known as a slurry) to the wafer surface while polishing the surface. The solution may include additives that chemically react with the surface material. CMP is widely used to planarize dielectric layers to provide a smooth surface for printing wiring patterns.
A CMP application, known as the Damascene process, provides a planar surface with a wiring pattern embedded in an insulating layer, such as SiO.sub.2. The embedded wiring pattern is formed by first etching grooves into, but not through, the insulating layer. If the Damascene process is used to form vias instead of grooves, holes are opened through the insulating layer. Once the pattern is formed, a conformal metal layer is deposited onto the patterned surface. The conformal metal layer is chem-mech polished to remove all metal above the insulating layer. After polishing, metal remains only in the patterned grooves or in the holes in the insulating layer. Metal is completely removed from areas that have no grooves or holes, i.e., fields.
Currently, Damascene is preferred to Reactive Ion Etching (RIE) for forming aluminum alloy lines and vias for intra-chip wiring. Normally, the metal layer is an aluminum alloy formed on a thin liner. The liner is formed prior to the high temperature reflow step, when a 200-300 .ANG. thick layer is deposited on the patterned dielectric surface. Next, part or all of the alloy layer, usually Al--Cu or Al--Cu--Si, is deposited on the liner at high temperature, about 500.degree. C. If the liner is titanium, it absorbs oxygen at via interfaces, thereby preventing formation of aluminum oxide and insuring low via contact resistance. Titanium has this oxygen-gettering property because it solves about 10 atomic percent oxygen in its solid state. In addition to reduced via contact resistance, titanium promotes aluminum "flow" onto the liner in the Damascene process, because its oxygen-gettering property also prevents aluminum oxidation. Unfortunately, Damascene process includes both a high temperature reflow step and a CMP step. In both of these steps, a titanium liner also has distinct handicaps.
The first handicap is that during the high temperature reflow step, most of the liner and some of the aluminum is consumed as it combines to form TiAl.sub.3. During the high temperature step, typically, most of the 200 .ANG.-300 .ANG. titanium liner forms 600 .ANG.-900 .ANG. of TiAl.sub.3, with a much thinner titanium-rich film remaining at the dielectric interface. TiAl.sub.3 has a much higher resistivity than aluminum, around 70 .mu..OMEGA..multidot.cm. Thus, because this TiAl.sub.3 also consumes Al, it reduces the thickness of the aluminum, so that line sheet resistance increases.
FIGS. 1A-C represent Damascene reflow and polishing of a semiconductor structure. In FIG. 1A, aluminum alloy was deposited onto patterned SiO.sub.2 layer 102. The pattern recesses are typically 0.25 .mu.m wide and 0.5 .mu.m deep. The continuous aluminum layer 100 above the dielectric is thinner over the arrays (of lines) than over more sparsely patterned fields (hereinafter "fields"), because alloy from the layer 100 fills trenches 104 in the array, as identified by reference 108. If the width of the trenches 104 (i.e., the metal lines) and the width of the insulator spaces 106 are equal in the arrays 108, then the continuous aluminum film 100 is thinner by half the trench-depth (i.e., the average surface depression) in the arrays 108, than over the adjacent fields, as identified by reference 110.
Next, the surface aluminum alloy layer 100 is removed in a CMP step. As depicted in FIG. 1B, overpolishing during CMP may cause erosion of the narrow SiO.sub.2 spaces in the arrays 108. This is because the aluminum layer 100 is much thicker in the fields 110 than in the arrays 108. So, in this case, completely polishing the aluminum alloy away from the fields 110 causes the patterned array area 108 to be overpolished, because polishing continues long after the aluminum layer 100 has been cleared away. Consequently, the array line thickness 112 is much less than field line thickness (not shown), and much less than desired 114. Since pattern depth determines metal line thickness, the erosion from this overpolishing causes thinner array metal lines resulting in higher array wiring (line) resistance.
Continuing the previous example in FIG. 1C, if the starting line depth was 0.5 .mu.m, then because of overpolishing in the CMP step, the thickness of the metal 116 remaining in the polished array trenches 104 may be as thin as 0.25 .mu.m deep. Further, of this 0.25 .mu.m, as much as 0.1 .mu.m may have been converted to low conductivity TiAl.sub.3 117. So, the remaining high conductivity aluminum alloy 118 is only 0.15 .mu.m thick.
Consequently, because Al is consumed as TiAl.sub.3 during high temperature treatment and further because of overpolishing, it is difficult to lower line sheet resistance in arrays. Low line sheet resistance is a requirement for making acceptable wiring resistance. Further, this consumption of Al makes uniform wiring sheet resistance across a chip, much less across a wafer, an impossible goal.